Missing CCP Compare Mode for PIC18?

[Max Peelman]

I have an application using a PIC18F252 where I want to toggle the output state of a pin every X seconds, where X varies according to input conditions. According to the Microchip documentation for configuring the CCPxCON register there is an additional Compare mode not included with the PIC16 devices that Toggles the output pin state on a Compare match. However when I look at "PIC18F252.h" a constant is not supplied for this mode (value = 2) and when I pass 2 to setup_ccpx() the expected action does not occur.
Have I overlooked something? I checked the latest data sheet and the errata and didn't see anything about this mode not truly being supported.
Thanks!
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This message was ported from CCS's old forum
Original Post ID: 7117

[R.J.Hamlett]

:= I have an application using a PIC18F252 where I want to toggle the output state of a pin every X seconds, where X varies according to input conditions. According to the Microchip documentation for configuring the CCPxCON register there is an additional Compare mode not included with the PIC16 devices that Toggles the output pin state on a Compare match. However when I look at "PIC18F252.h" a constant is not supplied for this mode (value = 2) and when I pass 2 to setup_ccpx() the expected action does not occur.
:= Have I overlooked something? I checked the latest data sheet and the errata and didn't see anything about this mode not truly being supported.
:= Thanks!

First, have a look at the LST file, and see if the code is being generated as expected. It should have something like:
MOVLW 02
MOVWF FBD

(assuming you are using CCP1).
If this is correct (I can see no reason why it should be wrong), then the problem has to be somewhere else in the code.
Obvious thoughts are:
1) Are you setting the port for FAST_IO, and clearing this bit in the TRIS register so the pin is an output?.
2) Is the timer you are using running as a synchronised counter, or as a timer?. If not, there would be problems.

I'd start by verifying that the rest of the code works, with the pin programmed to go high (say), and adding a small routine on the interrupt flag being set, to clear the pin again. If you get the expected 'pulse' on compare, you have verified the rest of the code. At this point, be 'brutal', and look through your list file to find the statement setting it to the other value (say):

MOVLW 08
MOVWF FBD

find the address of the first instruction, and then with that address known as (say) 1000, add a line like:

#ROM 0x1000 = {0x0e02}

If I have got this right, it should substitute your required instruction, for the current one, _without_ changing anything else for the compiler. If this then works, the fault is in the compiler somewhere. If however it fails, then the problem is with the chip.

Best Wishes
___________________________
This message was ported from CCS's old forum
Original Post ID: 7118

[Max Peelman]

:=
:=First, have a look at the LST file, and see if the code is being generated as expected. It should have something like:
:=

OK, I think I've found a problem with the compiler v3.110. In my application I am using CCP1 for monitoring an input and CCP2 for updating a frequency output. To keep the two independent from each other I want to have CCP1 use TMR1 as its timebase and CCP2 use TMR3. Since no constant was provided for value 0x02 for CCP2CON in "PIC18F252.h" I thought it best to not try the Toggle Compare mode until I proved that my application worked by toggling the CCP2 Compare Set/Reset modes myself in my ISR. Therefore initial software looks like:

Program startup:
setup_ccp2 (CCP_COMPARE_SET_ON_MATCH | CCP_USE_TIMER3);

ISR:
if ( input(FREQ_OUTPUT_PIN) )
{
setup_ccp2 (CCP_COMPARE_CLR_ON_MATCH | CCP_USE_TIMER3);
}
else
{
setup_ccp2 (CCP_COMPARE_SET_ON_MATCH | CCP_USE_TIMER3);
}

This works but does what the Toggle Compare mode should do automatically, so I remarked out the above ISR code and changed the Program startup code to:

Program startup:
setup_ccp2 (2 | CCP_USE_TIMER3);

This causes my application to stop working correctly and upon inspecting the LST file for both versions I found the following ASM code for each version (the comments are mine):

First (working) version:
BCF F8B.1 ; F8B=LATC
MOVLW B7
ANDWF FB1,F ; FB1=T3CON
BSF FB1.3
MOVLW 08
MOVWF FBA ; FBA=CCP2CON

Second (non-working) version:
BCF F82.1 ; F82=PORTC
CLRF FBA ; FBA=CCP2CON
MOVLW 02
MOVWF FBA

The difference is that TMR3 is not configured as the timebase for CCP2. I created another version where I left the ISR code remarked out and modified the Program startup code to:

Program startup:
#asm ASIS
BCF 0xF8B.1 ; F8B=LATC
MOVLW 0xB7
ANDWF 0xFB1,F ; FB1=T3CON
BSF 0xFB1.3
MOVLW 0x02
MOVWF 0xFBA ; FBA=CCP2CON
#endasm

...and this version works!
Sorry for the length of the post but I was hoping to be descriptive enough to illustrate the issue.
Thanks!
___________________________
This message was ported from CCS's old forum
Original Post ID: 7119

[R.J.Hamlett]

:=:=
:=:=First, have a look at the LST file, and see if the code is being generated as expected. It should have something like:
:=:=
:=
:= OK, I think I've found a problem with the compiler v3.110. In my application I am using CCP1 for monitoring an input and CCP2 for updating a frequency output. To keep the two independent from each other I want to have CCP1 use TMR1 as its timebase and CCP2 use TMR3. Since no constant was provided for value 0x02 for CCP2CON in "PIC18F252.h" I thought it best to not try the Toggle Compare mode until I proved that my application worked by toggling the CCP2 Compare Set/Reset modes myself in my ISR. Therefore initial software looks like:
:=
:= Program startup:
:= setup_ccp2 (CCP_COMPARE_SET_ON_MATCH | CCP_USE_TIMER3);
:=
:= ISR:
:= if ( input(FREQ_OUTPUT_PIN) )
:= {
:= setup_ccp2 (CCP_COMPARE_CLR_ON_MATCH | CCP_USE_TIMER3);
:= }
:= else
:= {
:= setup_ccp2 (CCP_COMPARE_SET_ON_MATCH | CCP_USE_TIMER3);
:= }
:=
:= This works but does what the Toggle Compare mode should do automatically, so I remarked out the above ISR code and changed the Program startup code to:
:=
:= Program startup:
:= setup_ccp2 (2 | CCP_USE_TIMER3);
:=
:= This causes my application to stop working correctly and upon inspecting the LST file for both versions I found the following ASM code for each version (the comments are mine):
:=
:= First (working) version:
:= BCF F8B.1 ; F8B=LATC
:= MOVLW B7
:= ANDWF FB1,F ; FB1=T3CON
:= BSF FB1.3
:= MOVLW 08
:= MOVWF FBA ; FBA=CCP2CON
:=
:= Second (non-working) version:
:= BCF F82.1 ; F82=PORTC
:= CLRF FBA ; FBA=CCP2CON
:= MOVLW 02
:= MOVWF FBA
:=
:= The difference is that TMR3 is not configured as the timebase for CCP2. I created another version where I left the ISR code remarked out and modified the Program startup code to:
:=
:= Program startup:
:= #asm ASIS
:= BCF 0xF8B.1 ; F8B=LATC
:= MOVLW 0xB7
:= ANDWF 0xFB1,F ; FB1=T3CON
:= BSF 0xFB1.3
:= MOVLW 0x02
:= MOVWF 0xFBA ; FBA=CCP2CON
:= #endasm
:=
:= ...and this version works!
:= Sorry for the length of the post but I was hoping to be descriptive enough to illustrate the issue.
:= Thanks!
Well done.
You were obviously thinking along the same lines as me, that the unknown constant, changes the way the compiler behaves (this is why I was suggesting patching the single line in the generated code with the #ROM statement).
Unfortunately, it is not just the 'text' being unrecognised, but the value as well (you can try this, by changing the value of 'CCP_COMPARE_SET_ON_MATCH', to 2 in the .h file.
Your demo, shows this excellently, and you should send this to CCS (definately a bug).

Best Wishes
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This message was ported from CCS's old forum
Original Post ID: 7122