Problem with inline assembly in PCH ver 3.114

Ivar Johnsrud · Guest

Hi!

I am developing a real time os to pic18 series of chips, and because I need 100\% control of several parts of the program, I am using a lot of inline assembly. I have experienced that PCH is not accepting the access bank bit which is added on many instructions in the 16 bit series of chips. Ie the movf f,d,a instruction will not compile with the a as 0 or 1. Without it, it will compile. Anyone else had problems with this? Anyone know if PCH will auto select this bit, or default it to anything? I looked at the documentation of the #asm directive, and there all the instructions were listed on f,d,a form.
 
Thanks, Ivar
 
This sample code does nothing, but illustrates the problem.


<pre>
 #include <18f452.h>
 
 #define FSR0H 0xFEA
 #define FSR0L 0xFE9
 #define WREG 0xFE8
 
 int offset;
 #locate offset=0x005 // Locate file in access ram.
 
 void main() {
 
 offset = 0x20;
 
 #asm
 
 movf FSR0H, 0
 subwf offset, 0, 0 // #error: Expecting an opcode mnemonic.
 movff WREG, FSR0H
 
 #endasm
 } 
</pre>


___________________________
This message was ported from CCS's old forum
Original Post ID: 7823

R.J.Hamlett · Guest

:=Hi!
:=
:=I am developing a real time os to pic18 series of chips, and because I need 100\% control of several parts of the program, I am using a lot of inline assembly. I have experienced that PCH is not accepting the access bank bit which is added on many instructions in the 16 bit series of chips. Ie the movf f,d,a instruction will not compile with the a as 0 or 1. Without it, it will compile. Anyone else had problems with this? Anyone know if PCH will auto select this bit, or default it to anything? I looked at the documentation of the #asm directive, and there all the instructions were listed on f,d,a form.
:= 
:=Thanks, Ivar
:= 
:=This sample code does nothing, but illustrates the problem.
:=
:=
:=<pre>
:= #include <18f452.h>
:= 
:= #define FSR0H 0xFEA
:= #define FSR0L 0xFE9
:= #define WREG 0xFE8
:= 
:= int offset;
:= #locate offset=0x005 // Locate file in access ram.
:= 
:= void main() {
:= 
:= offset = 0x20;
:= 
:= #asm
:= 
:= movf FSR0H, 0
:= subwf offset, 0, 0 // #error: Expecting an opcode mnemonic.
:= movff WREG, FSR0H
:= 
:= #endasm
:= } 
:=</pre>
:=
:=
I had a similar problem with RETFIE, a few versions ago, which would not accept the '1' option. Asked CCS, and they updated the assembler to allow this. It is worth realising, that this will be very complex, since the compiler makes significant use of the access RAM itself. I'm afraid you'll have to ask CCS for a fix. If you only want a couple of instructions, you can add a #ROM address={value} statement latter to modify the code generated to include the extra bit.
The default is rather odd. The code given, actually generates the value 5500, which is a subwfb instruction (rather than a subwf), with the access bank disabled.

Best Wishes
___________________________
This message was ported from CCS's old forum
Original Post ID: 7828

shep · Guest

:=Hi!
:=
:=I am developing a real time os to pic18 series of chips, and because I need 100\% control of several parts of the program, I am using a lot of inline assembly. I have experienced that PCH is not accepting the access bank bit which is added on many instructions in the 16 bit series of chips. Ie the movf f,d,a instruction will not compile with the a as 0 or 1. Without it, it will compile. Anyone else had problems with this? Anyone know if PCH will auto select this bit, or default it to anything? I looked at the documentation of the #asm directive, and there all the instructions were listed on f,d,a form.
:= 
:=Thanks, Ivar
:= 
:=This sample code does nothing, but illustrates the problem.
:=
:=
:=<pre>
:= #include <18f452.h>
:= 
:= #define FSR0H 0xFEA
:= #define FSR0L 0xFE9
:= #define WREG 0xFE8
:= 
:= int offset;
:= #locate offset=0x005 // Locate file in access ram.
:= 
:= void main() {
:= 
:= offset = 0x20;
:= 
:= #asm
:= 
:= movf FSR0H, 0
:= subwf offset, 0, 0 // #error: Expecting an opcode mnemonic.
:= movff WREG, FSR0H
:= 
:= #endasm
:= } 
:=</pre>
:=
:=

No idea about your problem, but i like your sig Smile

___________________________
This message was ported from CCS's old forum
Original Post ID: 7832