F877 Timer 1 overflow

[Jeff Stevens]

I'm trying to use timer1 to measure the period of a signal on RC0. Timer 1 is configured as such:

SETUP_TIMER_1(T1_INTERNAL|T1_DIV_BY_2); // Configure 16 bit timer1

and the oscillator is 4Mhz ( 1µsecond instruction cycle ).

With the divide-by-2 prescale on a 16 bit timer, I'm expecting the timer1 overflow flag (TMR1IF) to be set after 131072 µseconds (65536 µseconds * 2). Instead, I'm finding that it gets set when the count is 32768 ( still 65536 µseconds ). No matter the divide-by value, the flag is set after 65536 µseconds.

Can anyone offer some insight into what might be happening?

Thanks in advance. ~ Jeff
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This message was ported from CCS's old forum
Original Post ID: 8387

[PCM programmer]

:=I'm trying to use timer1 to measure the period of a signal on RC0. Timer 1 is configured as such:
:=
:=SETUP_TIMER_1(T1_INTERNAL|T1_DIV_BY_2); // Configure 16 bit timer1
:=
:=and the oscillator is 4Mhz ( 1µsecond instruction cycle ).
:=
:=With the divide-by-2 prescale on a 16 bit timer, I'm expecting the timer1 overflow flag (TMR1IF) to be set after 131072 µseconds (65536 µseconds * 2). Instead, I'm finding that it gets set when the count is 32768 ( still 65536 µseconds ). No matter the divide-by value, the flag is set after 65536 µseconds.
:=
--------------------------------------------------

Can you post a short, but complete demo program that demonstrates the problem ? (Please include all pre-processor statements).

The common method for measuring the time between two pulses
is to use the CCP capture mode. I don't think you're doing
it that way, so please give an explanation of what you're
doing, and why, along with your demo program.
___________________________
This message was ported from CCS's old forum
Original Post ID: 8413

[Jeff Stevens]

:=:=I'm trying to use timer1 to measure the period of a signal on RC0. Timer 1 is configured as such:
:=:=
:=:=SETUP_TIMER_1(T1_INTERNAL|T1_DIV_BY_2); // Configure 16 bit timer1
:=:=
:=:=and the oscillator is 4Mhz ( 1µsecond instruction cycle ).
:=:=
:=:=With the divide-by-2 prescale on a 16 bit timer, I'm expecting the timer1 overflow flag (TMR1IF) to be set after 131072 µseconds (65536 µseconds * 2). Instead, I'm finding that it gets set when the count is 32768 ( still 65536 µseconds ). No matter the divide-by value, the flag is set after 65536 µseconds.
:=:=
:=--------------------------------------------------
:=
:=Can you post a short, but complete demo program that demonstrates the problem ? (Please include all pre-processor statements).
:=
:=The common method for measuring the time between two pulses
:=is to use the CCP capture mode. I don't think you're doing
:=it that way, so please give an explanation of what you're
:=doing, and why, along with your demo program.

Okay, my bad. The problem was not the timer, but the device that produces the pulses. It wouldn't configure itself if the pulse period was a µsecond too long.
And thanks for reminding me of CCP capture mode. I'm going to use it. ~ Odd how one sometimes can't see the forest for the trees.
___________________________
This message was ported from CCS's old forum
Original Post ID: 8602